FIG. 6 is a block diagram schematically illustrating the hardware configuration of a conventional information processor.
An information processor 300 depicted in FIG. 6 includes one or more (two in the example of FIG. 6) CPUs 301a and 301b, one or more (two in the example of FIG. 6) memories 302a and 302b, chipsets 303 and 304, a PCI device 305, and an I/O device 306.
The CPUs 301a and 301b realize various functions and controls through the execution of programs.
The memories 302a and 302b temporarily store various pieces of data and programs for execution of the programs in the CPUs 301a and 301b. 
The chipset 303 (North Bridge) controls connection of the CPUs 301a and 301b to the memories 16a and 16b. The chipset 303 includes a memory controller 307, through which the memories 302a and 302b are controlled.
In the example of FIG. 6, to the chipset 303, the PCI device 305 is connected, so that the chipset 303 controls the connection of the PCI device 305 and the chipset 303.
The chipset 304 (South Bridge) serves as an integration of various I/O (Input/Output) controllers and is communicably connected to the chipset 303. In the example of FIG. 6, to the chipset 304, the I/O device 306 is connected.
The I/O device 306 is a peripheral device used in an information processor and is exemplified by a CompactFlash (trademark) or a BIOS flash.
The example of FIG. 6 illustrates a state of an error handler 308 being expanded (stored) in the memory 302a. The error hander 308 is a program (a code, a handler) to handle a possible abnormality (error) which occurs in either the memory 302a or 302b during the operation of the information processor 300, and is executed by the CPU 301a. 
An error (a memory error) may occur in the memory 302a or 302b in the conventional information processor 300.
For example, in the disclosure of the patent reference 1 below, if an uncorrectable error occurs, an ECC (Error Correction Code) error handler allocates a new page; copies data of a page on which the error has occurred to the new page; and makes the page with the error disable. Thereby the patent reference 1 prevents the system from hanging up even if an uncorrectable error occurs.
[Patent Reference 1] Japanese Patent Application Laid-Open (KOKAI) No. HEI 5-204770
However, in the above conventional information processor 300, the error handler 308 cannot sufficiently handle an error in some case.
For example, if an uncorrectable error occurs in the memory 302a, there is a high possibility that an error may occur at another points on the same memory (i.e., the memory 302a).
Accordingly, while the error handler 308 is being executed to handle the memory uncorrectable error, if another memory uncorrectable error occurs, the execution code of the error handler 308 expanded on the same memory 302a may come to be abnormal, causing a hang. In the event that the error handler hangs up, it is impossible to identify the point of occurrence of the error.
Further, if an error occurs during the system operation in the information processor 300, the CPU 301a (error handler 308) extracts information from each of the devices installed in the information processor 300 so that the point of occurrence of the error is identified on the basis of the extracted information.
However, when the CPU 301a accesses a device to extract information from the device and the device has an error, the system may hang up (freezes). A hang occurred while the CPU 301a is extracting information from a device, the CPU 301a cannot extract information from the remaining device, so that a point of occurrence of the error cannot be identified.
Further, if a system hangs up, the conventional information processor cannot judge whether the hang of the system has been caused by the device being accessed by the CPU 301a or by the CPU 301a itself. Consequently, the point of occurrence or the error cannot also be identified.